參數資料
型號: MR80C32-25/883R
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁數: 147/182頁
文件大?。?/td> 2994K
代理商: MR80C32-25/883R
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67
1477K–AVR–08/10
ATtiny26(L)
The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are
scaled directly from the CK oscillator clock. If the external pin modes are used, the correspond-
ing setup must be performed in the actual Data Direction Control Register (cleared to zero gives
an input pin).
Timer/Counter0 –
TCNT0
The Timer/Counter0 is implemented as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting
in the timer clock cycle following the write operation.
8-bit
Timer/Counter1
The Timer/Counter1 has two clocking modes: a synchronous mode and an asynchronous mode.
The synchronous mode uses the system clock (CK) as the clock timebase and asynchronous
mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from the
PLLCSR Register enables the asynchronous mode when it is set (“1”). The Timer/Counter1 gen-
eral operation is described in the asynchronous mode and the operation in the synchronous
mode is mentioned only if there is differences between these two modes. Figure 39 shows
Timer/Counter1 synchronization register block diagram and synchronization delays in between
registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 Reg-
ister values go through the internal synchronization registers, which cause the input
synchronization delay, before affecting the counter operation. The registers TCCR1A, TCCR1B,
OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back
values are delayed for the Timer/Counter1 (TCNT1) Register and flags (OCF1A, OCF1B, and
TOV1), because of the input and output synchronization.
This module features a high resolution and a high accuracy usage with the lower prescaling
opportunities. Timer/Counter1 can also support two accurate, high speed, 8-bit Pulse Width
Modulators using clock speeds up to 64 MHz. In this mode, Timer/Counter1 and the Output
Compare Registers serve as dual stand-alone PWMs with non-overlapping non-inverted and
inverted outputs. Refer to page 74 for a detailed description on this function. Similarly, the high
prescaling opportunities make this unit useful for lower speed functions or exact timing functions
with infrequent actions.
Bit
765
4321
0
$32 ($52)
MSB
LSB
TCNT0
Read/Write
R/W
Initial Value
000
0000
0
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