參數(shù)資料
型號: MR1A08AYS35
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM
中文描述: 64K的x 16位的3.3V異步磁阻隨機(jī)存取內(nèi)存
文件頁數(shù): 9/20頁
文件大?。?/td> 148K
代理商: MR1A08AYS35
Timing Specifications
MR0A16A Advanced Information Data Sheet, Rev. 0
Freescale Semiconductor
9
Write Mode
Table 10. Write Cycle Timing 1 (W Controlled)
1, 2, 3, 4, 5
Parameter
Symbol
t
AVAV
t
AVWL
t
AVWH
t
AVWH
t
WLWH
t
WLEH
t
WLWH
t
WLEH
t
DVWH
t
WHDX
t
WLQZ
t
WHQX
t
WHAX
Min
35
0
18
20
Max
Unit
ns
ns
ns
ns
Write cycle time
6
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Write pulse width (G high)
15
ns
Write pulse width (G low)
15
ns
Data valid to end of write
Data hold time
Write low to data Hi-Z
7, 8, 9
Write high to output active
7, 8, 9
Write recovery time
10
0
0
3
12
12
ns
ns
ns
ns
ns
NOTES:
1
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested.
Transition is measured
±
200 mV from steady-state voltage.
At any given voltage or temperature, t
WLQZ
max < t
WHQX
min.
2
3
4
5
6
7
8
9
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