
1066
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode, this signal is syn-
chronized with the first active LCDDOTCK rising edge in a line.
In TFT mode, the high phase of this signal starts at the beginning of the first line. The following timing parameters
can be selected:
Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register. The
pulse width is equal to (VPW+1) lines.
Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of
LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in STN
Mode.
Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of LCDTIM2
register. The number of inactive lines is equal to VFP. This field should be programmed with 0 in STN mode.
There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the
LCDFRMCFG:
HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in each
line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.
LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The
minimum value of this parameter is 1.
signals:
Figure 45-5. STN Panel Timing, CLKMOD 0
LCDHSYNC
LCDVSYNC
LCDDEN
LCDDOTCK
LCDD
Frame Period
VHDLY+
HBP+1
HPW+1
HFP+VHDLY+2
HOZVAL+1
LCDDOTCK
LCDD
1 PCLK
1/2 PCLK 1/2 PCLK
Line Period
LCDVSYNC
LCDHSYNC
LCDDEN