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型號(hào)：	MQ80C32-20
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 20 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁(yè)數(shù)：	75/1185頁(yè)
文件大小：	5451K
代理商：	MQ80C32-20

SAM9G45 [DATASHEET]

6438K–ATARM–12-Feb-13

The LCDDEN signal indicates valid data in the LCD Interface.

After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be

displayed on the panel.

The following timing parameters can be configured:

Vertical to Horizontal Delay (VHDLY): The delay between the falling edge of LCDVSYNC and the generation of

LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to (VHDLY+1)

LCDDOTCK cycles.

Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of LCDTIM2 register.

The width is equal to (HPW + 1) LCDDOTCK cycles.

Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first LCDDOTCK rising

edge with valid data at the LCD Interface is configurable in the HBP field of the LCDTIM2 register. The delay is

equal to (HBP+1) LCDDOTCK cycles.

Horizontal Front Porch (HFP): The delay between end of valid data and the generation of the next LCDHSYNC

is configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+VHDLY+2) LCDDOTCK

There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by the initial latency of

the datapath. The total delay in LCDC clock cycles must be higher than or equal to the latency column in Table 45-

4 on page 1058. This limitation is given by the following formula:

VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers

PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles

DPATH_LATENCY is the datapath latency of the configuration, given in Table 45-4 on page 1058

The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at

the top of the display. The timing of this signal depends on the type of LCD: STN or TFT LCD.

Table 45-14. Minimum LCDDOTCK Period in LCDC Core Clock Cycles

Configuration

LCDDOTCK Period

() PCLK_PERIOD

DPATH_LATENCY

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