參數(shù)資料
型號(hào)： MPR081QR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, QCC16
封裝： 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, QFN-16
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 324K
代理商： MPR081QR2
MPR081
Sensors
Freescale Semiconductor
15
Table 19. Configuration Register Format
Register
R/W
Register
Address
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
Read Configuration Register
1
0x09
Interrupt Rate
RESET N/A WAKE IRQEN
RUN
Write Configuration Register
0
MPR081 is in shutdown, and will not scan the rotary.
Note that FIFO contents are not cleared when entering shutdown
and can be read any time during shutdown.
X
1
X
0
MPR081 is operating, scanning the rotary, with IRQ interrupt
output disabled. Poll the FIFO register 0x00 and/or the Current
Rotary register 0x02 to determine current rotary status.
Note that FIFO contents are cleared before exiting shutdown
X
1
X
0
1
MPR081 is operating, scanning the rotary, with IRQ interrupt
output enabled. IRQ behavior is controlled by Interrupt Rate bits
D5-D7, and is asserted on the first entry into the FIFO from
empty.
Note that FIFO contents are cleared before exiting shutdown
X
1
X
1
MPR081 will go into low power sleep mode after an idle period
timeout. While in low power sleep mode, device cannot be
addressed via I2C except by asserting the wake pin.
X
1
X
0
1
X
MPR081 will remain awake and can be addressed at anytime via
I2C.
X
1
X
1
X
System reset asserted. MPR081 can be addressed via I2C at
anytime.
X
0
X
1
System reset de-asserted. MPR081 can be addressed via I2C at
anytime.
X
1
X
1
IRQ interrupt is immediate when FIFO changes from empty
0
1
X
1
IRQ interrupt asserts no sooner than 4 master tick periods after
the last IRQ rise
0
1
X
1
IRQ interrupt asserts no sooner than 12 master tick periods after
the last IRQ rise
0
1
0
1
X
1
IRQ interrupt asserts no sooner than 20 master tick periods after
the last IRQ rise
0
1
X
1
IRQ interrupt asserts no sooner than 28 master tick periods after
the last IRQ rise
1
0
1
X
1
IRQ interrupt asserts no sooner than 36 master tick periods after
the last IRQ rise
1
0
1
X
1
IRQ interrupt asserts no sooner than 44 master tick periods after
the last IRQ rise
1
0
1
X
1
IRQ interrupt asserts no sooner than 52 master tick periods after
the last IRQ rise
1
X
1
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