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參數(shù)資料
| 型號： | MPR081QR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, QCC16 |
| 封裝： | 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, QFN-16 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 324K |
| 代理商： | MPR081QR2 |
MPR081
Sensors
Freescale Semiconductor
7
SERIAL INTERFACE
SERIAL-ADDRESSING
The MPR081 operates as a slave that sends and receives
data through an I2C 2-wire interface. The interface uses a
serial data line (SDA) and a serial clock line (SCL) to achieve
bi-directional communication between master(s) and
slave(s). A master (typically a microcontroller) initiates all
data transfers to and from the MPR081 and generates the
SCL clock that synchronizes the data transfer.
Figure 4. 2-Wire Serial Interface Timing Details
The MPR081 SDA line operates as both an input and an
open-drain output. A pull-up resistor, typically 4.7 k
Ω, is
required on SDA. The MPR081 SCL line operates only as an
input. A pull-up resistor, typically 4.7 k
Ω, is required on SCL if
there are multiple masters on the 2-wire interface, or if the
master in a single-master system has an open-drain SCL
output.
Each transmission consists of a START condition
(Figure 5) sent by a master, followed by the MPR081's 7-bit
slave address plus R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
Figure 5. Start and Stop Conditions
START AND STOP CONDITIONS
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission with a
START (S) condition by transitioning SDA from high to low
while SCL is high. When the master has finished
communicating with the slave, it issues a STOP (P) condition
by transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission.
BIT TRANSFER
One data bit is transferred during each clock pulse
(Figure 6). The data on SDA must remain stable while SCL is
high.
Figure 6. Bit Transfer
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