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參數資料
| 型號： | MPE603PRX166LX |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 167 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CBGA-255 |
| 文件頁數： | 5/36頁 |
| 文件大?。?/td> | 411K |
| 代理商： | MPE603PRX166LX |
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PRELIMINAR
Y
PID7v-EC603e Hardware Specifications
13
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1.4.3 JTAG AC Timing Specications
Table 9 provides the JTAG AC timing specications as dened in Figure 5 through Figure 8.
Figure 5 provides the JTAG clock input timing diagram.
Figure 5. JTAG Clock Input Timing Diagram
Table 9. JTAG AC Timing Specifications
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0 ≤ Tj ≤ 105° C, C
L = 50 pF
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
16
MHz
1
TCK cycle time
62.5
—
ns
2
TCK clock pulse width measured at 1.4 V
25
—
ns
3
TCK rise and fall times
0
3
ns
4
TRST setup time to TCK rising edge
13
—
ns
1
5
TRST assert time
40
—
ns
6
Boundary scan input data setup time
6
—
ns
2
7
Boundary scan input data hold time
27
—
ns
2
8
TCK to output data valid
4
25
ns
3
9
TCK to output high impedance
3
24
ns
3
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
25
—
ns
12
TCK to TDO data valid
4
24
ns
13
TCK to TDO high impedance
3
15
ns
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
TCK
2
1
VM
3
VM = Midpoint Voltage (1.4 V)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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ARCHIVED
BY
FREESCALE
SEMICONDUCT
OR,
INC.
2006
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