參數(shù)資料
型號(hào)： MPE603PRX166LX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 167 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 1.27 MM PITCH, CBGA-255
文件頁(yè)數(shù)： 3/36頁(yè)
文件大?。?/td> 411K
代理商： MPE603PRX166LX
PRELIMINAR
Y
PID7v-EC603e Hardware Specifications
11
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1.4.2.3 Output AC Specications
Table 8 provides the output AC timing specications for the PID7v-EC603e as dened in Figure 4.
Table 8. Output AC Timing Specifications1
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5%, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C, CL = 50 pF (unless otherwise noted)
Num
Characteristic
166 and 200 MHz
Unit
Notes
Min
Max
12
SYSCLK to output driven (output enable time)
1.0
—
ns
13a
SYSCLK to output valid (5.5 V to 0.8 V—TS, ABB, ARTRY, DBB)
—
9.0
ns
3
13b
SYSCLK to output valid (TS, ABB, ARTRY, DBB)
—
8.0
ns
5
14a
SYSCLK to output valid (5.5 V to 0.8 V—all except TS, ABB,
ARTRY, DBB)
—
11.0
ns
3
14b
SYSCLK to output valid (all except TS, ABB, ARTRY, DBB)
—
9.0
ns
5
15
SYSCLK to output invalid (output hold)
1.0
—
ns
2
16
SYSCLK to output high impedance (all except ARTRY, ABB, DBB)
—
8.5
ns
17
SYSCLK to ABB, DBB, high impedance after precharge
—
1.0
tsysclk
4,6
18
SYSCLK to ARTRY high impedance before precharge
—
8.0
ns
19
SYSCLK to ARTRY precharge enable
0.2 *
tsysclk + 1.0
—
ns
2,4,7
20
Maximum delay to ARTRY precharge
—
1.0
tsysclk
4,7
21
SYSCLK to ARTRY high impedance after precharge
—
2.0
tsysclk
5,7
Notes:
1. All output specications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V
or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. This minimum parameter assumes CL = 0 pF.
3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external
voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of
the parameter in question.
5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
7. Nominal precharge width for ARTRY is 1.0 tsysclk.
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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c
..
.
ARCHIVED
BY
FREESCALE
SEMICONDUCT
OR,
INC.
2006
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