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參數(shù)資料
| 型號(hào)： | MPC97H74AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
MPC97H74 REVISION 5 JANUARY 9, 2013
5
2013 Integrated Device Technology, Inc.
MPC97H74 Data Sheet
3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR
Table 8. PLL Frequency Ranges (VCC = 3.3 V ± 5%)
Symbol
Characteristics
TA = -40°C to +85°C
TA = 0°C to +70°C
Unit
Condition
Min
Max
Min
Max
fVCO
VCO Frequency Lock Range(1)
1. The input reference frequency must match the VCO frequency lock range divided by the total feedback divider ratio (FB): fREF = fVCO(M
VCO_SEL).
210
450
200
500
MHz
fREF
Input Reference Frequency Range
8 feedback
12 feedback
16 feedback
24 feedback
32 feedback
48 feedback
Input Reference Frequency Range in PLL Bypass Mode(2)
2. In bypass mode, the MPC97H74 divides the input reference clock.
26.250
17.500
13.125
8.750
6.5625
4.375
0
56.250
37.500
28.125
18.750
14.0625
9.375
250
25.0
16.6
12.5
8.33
6.25
4.16
0
62.50
41.60
31.25
20.83
15.625
10.41
250
MHz
PLL locked
PLL bypass
fMAX
Output Frequency Range
4 output
8 output
12 output
16 output
24 output
52.500
26.250
17.500
13.125
8.750
112.500
56.250
37.500
28.125
18.750
50.00
25.00
16.60
12.50
8.33
125.0
62.50
41.60
31.25
20.83
MHz
PLL locked
Table 9. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40°C to +85°C)
(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
tPW,MIN Input Reference Pulse Width(2)
2. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF, MIN. E.g. at fREF =62.5 MHz
the input duty cycle range is 12.5% < DC < 87.5%.
2.0
ns
tR, tF
CCLKx Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay (static phase offset)(3)
CCLKx to FB_IN (FB =
8 and fREF = 50 MHz)
3. Static phase offset depends on the reference frequency: t() = +50 ps (1 (120 fREF)) for any reference frequency.
–250
+100
ps
PLL locked
tSK(O)
Output-to-output Skew(4)
within QA bank
within QB bank
within QC bank
any output
4. Refer to Application section for part-to-part skew calculation.
100
125
100
175
ps
DC
Output Duty Cycle
47
50
53
%
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ Output Disable Time
10
ns
tPZL
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle Jitter(5)
5. Valid for all outputs at the same fequency.
90
ps
tJIT(PER) Period Jitter(4)
90
ps
tJIT()
I/O Phase Jitter RMS (1
)(6)
FB =
8
FB =
12
FB =
16
FB =
24
FB =
32
FB =
48
6. I/O jitter for fVCO = 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for
confidence factors other than 1
.
15
49
18
22
26
34
ps
BW
PLL Closed Loop Bandwidth(7)
FB =
8
FB =
12
FB =
16
FB =
24
FB =
32
FB =
48
7. –3 dB point of PLL transfer characteristics.
0.50 - 1.80
0.30 - 1.00
0.25 - 0.70
0.17 - 0.40
0.12 - 0.30
0.07 - 0.20
MHz
MHZ
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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