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參數(shù)資料
| 型號： | MPC97H74AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 標準包裝： | 1,500 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
MPC97H74 REVISION 5 JANUARY 9, 2013
3
2013 Integrated Device Technology, Inc.
MPC97H74 Data Sheet
3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK0
Input
LVCMOS PLL reference clock
CCLK1
Input
LVCMOS Alternative PLL reference clock
FB_IN
Input
LVCMOS PLL feedback signal input, connect to QFB
CCLK_SEL
Input
LVCMOS LVCMOS clock reference select
VCO_SEL
Input
LVCMOS VCO operating frequency select
PLL_EN
Input
LVCMOS PLL enable/PLL bypass mode select
MR/OE
Input
LVCMOS Output enable/disable (high-impedance tristate) and device reset
CLK_STOP
Input
LVCMOS Output enable/clock stop (logic low state)
FSEL_A
Input
LVCMOS Frequency divider select for bank A outputs
FSEL_B
Input
LVCMOS Frequency divider select for bank B outputs
FSEL_C
Input
LVCMOS Frequency divider select for bank C outputs
FSEL_FB[1:0] Input
LVCMOS Frequency divider select for the QFB output
QA[4:0]
Output LVCMOS Clock outputs (bank A)
QB[4:0]
Output LVCMOS Clock outputs (bank B)
QC[3:0]
Output LVCMOS Clock outputs (bank C)
QFB
Output LVCMOS PLL feedback output. Connect to FB_IN.
GND
Supply Ground
Negative power supply
VCC_PLL
Supply VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the
analog power supply pin VCC_PLL. Please see applications section for details.
VCC
Supply VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for
correct operation
Table 2. Function Table (MPC97H74 Configuration Controls)
Control
Default
0
1
CCLK_SEL
0
Selects CCLK0 as PLL reference signal input
Selects CCKL1 as PLL reference signal input
VCO_SEL
0
Selects VCO
2. The VCO frequency is scaled by a factor of 2
(high input frequency range)
Selects VCO
4. The VCO frequency is scaled
by a factor of 4 (low input frequency range).
PLL_EN
1
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC97H74 is fully static
and no minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
Normal operation mode with PLL enabled.
CLK_STOP
1
QA, QB an QC outputs disabled in logic low state. QFB is not
affected by CLK_STOP. CLK_STOP deassertion may cause the
initial output clock pulse to be distorted.
Outputs enabled (active)
MR/OE
1
Outputs disabled (high-impedance state) and reset of the device.
During reset/output disable the PLL feedback loop is open and
the internal VCO is tied to its lowest frequency. The MPC97H74
requires reset after any loss of PLL lock. Loss of PLL lock may
occur when the external feedback path is interrupted. The length
of the reset pulse should be greater than one reference clock
cycle (CCLKx). The device is reset by the internal power-on reset
(POR) circuitry during power-up.
Outputs enabled (active)
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.
Table 3. Function Table (Output Dividers Bank A, B, and C)
VCO_SEL
FSEL_A
QA[4:0]
VCO_SEL
FSEL_B
QB[4:0]
VCO_SEL
FSEL_C
QC[3:0]
0
VCO
4
0
VCO
4
0
VCO
8
0
1
VCO
8
0
1
VCO
8
0
1
VCO
12
1
0
VCO
8
1
0
VCO
8
1
0
VCO
16
1
VCO
16
1
VCO
16
1
VCO
24
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| MPC97H74FA | 功能描述:IC PLL CLK GENERATOR 1:14 52LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC980 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DUAL 3.3V PLL CLOCK GENERATOR |
| MPC9817 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers |
| MPC9817EN | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9817ENR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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