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參數(shù)資料
| 型號： | MPC97H73FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 206K |
| 代理商： | MPC97H73FAR2 |
MPC97H73
MOTOROLA
TIMING SOLUTIONS
12
Table 12. Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
Due to the frequency dependence of the static phase
offset and I/O jitter, using Figure 9. to Figure 11. to predict a
maximum I/O jitter and the specified t(
) parameter relative to
the input reference frequency results in a precise timing
performance analysis.
In the following example calculation an I/O jitter confidence
factor of 99.7% (
± 3s) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of -455 ps to +455 ps relative to CCLK (PLL
feedback =
÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps rms max., static
phase offset t() = ± 166 ps):
tSK(PP) =
[–166ps...166ps] + [–250ps...250ps] +
[(13ps
@ –3)...(13ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–455ps...455ps] + tPD, LINE(FB)
Figure 9. MPC9772 I/O Jitter
VCO frequency [MHz]
200
250
300
350
400
450 480
160
140
120
100
80
60
40
20
0
FB=÷32
FB=÷16
FB=÷8
FB=÷4
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
tjit(
)[ps]
RMS
Figure 10. MPC9772 I/O Jitter
VCO frequency [MHz]
200
250
300
350
400
450 480
120
100
80
60
40
20
0
FB=÷12
FB=÷24
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
tjit(
)[ps]
RMS
FB=÷6
Figure 11. MPC9772 I/O Jitter
VCO frequency [MHz]
200
250
300
350
400
450 480
140
120
100
80
60
40
20
0
FB=÷20
FB=÷10
FB=÷40
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
tjit(
)[ps]
RMS
Driving Transmission Lines
The MPC97H73 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC97H73 clock driver. For the series
terminated case however there is no DC current draw, thus
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