參數(shù)資料
型號(hào)： MPC97H73FAR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝： LQFP-52
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 206K
代理商： MPC97H73FAR2
MPC97H73
TIMING SOLUTIONS
7
MOTOROLA
Table 10. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a b
Symbol
Condition
Unit
Max
Typ
Min
Characteristics
BW
PLL closed loop bandwidthl
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20 - 3.50
0.70 - 2.50
0.50 - 1.80
0.45 - 1.20
0.30 - 1.00
0.25 - 0.70
0.20 - 0.55
0.17 - 0.40
0.12 - 0.30
0.11 - 0.28
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a
AC characteristics apply for parallel output termination of 50
to VTT.
b
The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF= fVCO ÷ (M VCO_SEL).
cVCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
d
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% - DCREF, MIN.
e
The MPC97H73 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can
only be guaranteed if tR, tF are within the specified range.
f
CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t() [s] = t() [°] ÷ (fREF 360°).
g
Excluding QSYNC output. See application section for part-to-part skew calculation.
h
Output duty cycle is DC = (0.5
± 200 ps fOUT) 100%. E.g. the DC range at fOUT=100MHz is 48%<DC<52%. T = output period.
i
Cycle jitter is valid for all outputs in the same divider configuration. See application section for more details.
j
Period jitter is valid for all outputs in the same divider configuration. See application section for more details.
k
I/O jitter is valid for a VCO frequency of 400 MHz. See application section for I/O jitter vs. VCO frequency.
l
-3 dB point of PLL transfer characteristics.
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