- 您現在的位置：買賣IC網 > PDF目錄26839 > MPC97H73FAR2 (FREESCALE SEMICONDUCTOR INC) PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 PDF資料下載
參數資料
| 型號： | MPC97H73FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數： | 20/20頁 |
| 文件大?。?/td> | 206K |
| 代理商： | MPC97H73FAR2 |
MPC97H73
TIMING SOLUTIONS
9
MOTOROLA
MPC97H73 Individual Output Disable (Clock Stop)
Circuitry
The individual clock stop (output enable) control of the
MPC97H73 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC97H73 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12–bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
The user can program an output clock to stop (disable) by
writing logic ‘0’ to the respective stop enable bit. Likewise, the
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would be in normally in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
The user can write to the serial input register through the
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free–running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC97H73 can sample each
STOP_DATA bit with the rising edge of the free–running
STOP_CLK signal. (see Figure 5. )
Figure 5. Clock Stop Circuit Programming
STOP_CLK
STOP_DATA
START QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
相關PDF資料 |
PDF描述 |
|---|---|
| MPC9893AE | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| MPC9894VFR2 | 9894 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA100 |
| MPC998FAR2 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC998FA | 998 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9990FAR2 | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC97H74AE | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC97H74AER2 | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC97H74FA | 功能描述:IC PLL CLK GENERATOR 1:14 52LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC980 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DUAL 3.3V PLL CLOCK GENERATOR |
| MPC9817 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復。