- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371135 > MPC974 (Motorola, Inc.) 3.3V PLL Clock Driver(3.3V PLL時(shí)鐘驅(qū)動(dòng)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC974 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V PLL Clock Driver(3.3V PLL時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 3.3V的PLL時(shí)鐘驅(qū)動(dòng)器（3.3鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器） |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | MPC974 |
MPC974
TIMING SOLUTIONS
BR1333 — Rev 6
5
MOTOROLA
Figure 3. MPC974 Programming Schemes
TCLK
FB_In
Qa
Qb
Qc
QFB
5
5
4
66MHz
66MHz
33MHz
33MHz
33MHz
fsela
0
fselb
0
fselc
0
fselFB
00
VCO_Sel
0
TCLK
FB_In
Qa
Qb
Qc
QFB
5
5
4
100MHz
50MHz
33MHz
33MHz
33MHz
fsela
0
fselb
1
fselc
1
fselFB
10
VCO_Sel
0
TCLK
FB_In
Qa
Qb
Qc
QFB
5
5
4
100MHz
50MHz
33MHz
25MHz
25MHz
fsela
0
fselb
1
fselc
1
fselFB
01
VCO_Sel
0
TCLK
FB_In
Qa
Qb
Qc
QFB
5
5
4
50MHz
50MHz
50MHz
50MHz
50MHz
fsela
1
fselb
1
fselc
0
fselFB
00
VCO_Sel
0
To minimize part–to–part skew the external feedback
option again should be used. The PLL in the MPC974
decouples the delay of the device from the propagation delay
variations of the internal gates. From the specification table
one sees a Tpd variation of only
±
150ps, thus for multiple
devices under identical configurations the part–to–part skew
will be around 850ps (300ps for Tpd variation plus 350ps
output–to–output skew plus 200ps for jitter). To minimize this
value, the highest possible reference frequencies should be
used. Higher reference frequencies will minimize both the tpd
parameter as well as the input to output jitter.
Power Supply Filtering
The MPC974 is a mixed analog/digital product and
exhibits some sensitivities that would not necessarily be seen
on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC974 provides separate
power supplies for the output buffers (VCCO) and the internal
PLL (VCCA) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC974.
Figure 4. Power Supply Filter
VCCA
VCC
MPC974
0.01
μ
F
22
μ
F
0.01
μ
F
3.3V
RS=5–15
Figure 4 illustrates a typical power supply filter scheme.
The MPC974 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC974. From the data sheet the IVCCA current
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 4 must have a resistance of 10–15
to meet
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9774 | 3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC980 | Dual 3.3V PLL Clock Generator(雙3.3V PLL時(shí)鐘發(fā)生器) |
| MPC9855 | Clock Generator for PowerQUICC and PowerPC Microprocessors |
| MPC992 | Low Voltage PLL Clock Driver(低壓PLL時(shí)鐘驅(qū)動(dòng)器) |
| MPC993 | Dynamic Switch PLL Clock Driver(動(dòng)態(tài)開(kāi)關(guān)PLL時(shí)鐘驅(qū)動(dòng)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC974A44 F44A WAF | 制造商:Motorola Inc 功能描述: |
| MPC9772 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:3.3V 1:12 LVCMOS PLL Clock Generator |
| MPC9772AE | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9772FA | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。