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參數(shù)資料
| 型號(hào)： | MPC961PACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 10/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER ZD 1:18 PLL 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 零延遲緩沖器 |
| PLL： | 是 |
| 輸入： | LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:17 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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MPC961P REVISION 5 JANUARY 8, 2013
6
2013 Integrated Device Technology, Inc.
MPC961P Data Sheet
LOW VOLTAGE ZERO DELAY BUFFER
APPLICATIONS INFORMATION
Power Supply Filtering
The MPC961P is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC961P provides separate
power supplies for the output buffers (VCC) and the phase-
locked loop (VCCA) of the device. The purpose of this design
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a controlled environment such as an evaluation board
this level of isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on the
power supplies, a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
VCCA pin for the MPC961P.
Figure 3 illustrates a typical power supply filter scheme.
The MPC961P is most susceptible to noise with spectral
content in the 10 kHz to 5 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the VCC supply and the VCCA
pin of the MPC961P. From the data sheet the ICCA current
(the current sourced through the VCCA pin) is typically 2 mA
(5 mA maximum), assuming that a minimum of 2.375 V
(VCC = 3.3 V or VCC = 2.5 V) must be maintained on the VCCA
resistance of 270
(VCC = 3.3 V) or 5 to 15 (VCC = 2.5 V)
to meet the voltage drop criteria. The RC filter pictured will
provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above
20 kHz. As the noise frequency crosses the series resonant
point of an individual capacitor it's overall impedance begins
to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown ensures
that a low impedance path to ground exists for frequencies
well above the bandwidth of the PLL.
Figure 3. Power Supply Filter
Although the MPC961P has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Driving Transmission Lines
The MPC961P clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 15
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091.
In most high performance clock networks point-to-point
distribution of signals is the method of choice. In a point-to-
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50
resistance to VCC/2. This technique draws a fairly high level
of DC current and thus only a single terminated line can be
driven by each output of the MPC961P clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC961P clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC961P output buffer is
more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC961P. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36
series resistor plus the
output impedance does not match the parallel combination of
VCCA
VCC
MPC961P
10 nF
RF = 270 for VCC = 3.3 V
RF = 5–15 for VCC = 2.5 V
CF
33...100 nF
RF
VCC
14
IN
MPC961
Output
Buffer
RS = 36
ZO = 50
OutA
14
IN
MPC961
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
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