參數資料
型號: MPC9600FA
廠商: MOTOROLA INC
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝: PLASTIC, LQFP-48
文件頁數: 9/12頁
文件大?。?/td> 180K
代理商: MPC9600FA
MPC9600
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
179
Table 5: AC CHARACTERISTICS (VCC = 3.3 V ±5% or VCC = 2.5 V ±5%, TA = –40° to +85°C)a
Symbol
Condition
Unit
Max
Typ
Min
Characteristics
tJIT(CC)
Cycle-to-cycle Jitterc
All outputs in
B2 configuration
All outputs in
B4 configuration
40
130
180
ps
See application
section for
other
configurations
tJIT(PER)
Period Jitterc
All outputs in
B2 configuration
All outputs in
B4 configuration
25
20
70
100
ps
See application
section for
other
configurations
tJIT()
I/O Phase Jitter (1
s)VCC = 3.3V
VCC = 2.5V
17d
15c
ps
RMS value at
fVCO=400MHz
tLOCK
Maximum PLL Lock Time
5.0
ms
a. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC characteris-
tics apply for parallel output termination of 50
to VTT.
b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
c. Cycle–to–cycle and period jitter depends on output divider configuration.
d. See applications section for max I/O phase jitter versus frequency.
2
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相關代理商/技術參數
參數描述
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