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參數(shù)資料
| 型號： | MPC9600FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | MPC9600FA |
MPC9600
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
183
of the MPC9600 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can
drive multiple series terminated lines. Figure 8 “Single versus
Dual Transmission Lines” illustrates an output driving a single
series terminated line versus two series terminated lines in
parallel. When taken to its extreme the fanout of the MPC9600
clock driver is effectively doubled due to its capability to drive
multiple lines.
Figure 8. Single versus Dual Transmission Lines
14
IN
MPC9600
OUTPUT
BUFFER
RS = 36
ZO = 50
14
IN
MPC9600
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots in Figure 9 “Single versus Dual Line
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases the
drive capability of the MPC9600 output buffer is more than suf-
ficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output-to-output skew of the
MPC9600. The output waveform in Figure 9 “Single versus
Dual Line Termination Waveforms” shows a step in the wave-
form, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36
se-
ries resistor plus the output impedance does not match the
parallel combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31 V
At the load end the voltage will double due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0 ns).
Figure 9. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 10 “Optimized Dual Line Termination” should be
used. In this case the series terminating resistors are reduced
such that when the parallel combination is added to the output
buffer impedance the line impedance is perfectly matched.
Figure 10. Optimized Dual Line Termination
14
MPC9600
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 k 22 = 50 k 50
25
= 25
2
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