- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26838 > MPC9600FA (MOTOROLA INC) PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 PDF資料下載
參數(shù)資料
| 型號： | MPC9600FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | MPC9600FA |
MPC9600
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
181
Figure 3. Configuration for 125 MHz clocks
Figure 4. Configuration for 133.3/66.67 MHz clocks
MPC9600
fref = 20.833 MHz
125 MHz
20.833 MHz (Feedback)
125 MHz
Frequency range
Min
Max
Input
16.67 MHz
33.33 MHz
QA outputs
100 MHz
200 MHz
QB outputs
100 MHz
200 MHz
QC outputs
100 MHz
200 MHz
Frequency range
Min
Max
Input
25 MHz
50 MHz
QA outputs
100 MHz
200 MHz
QB outputs
100 MHz
200 MHz
QC outputs
100 MHz
200 MHz
CCLK
FB_IN
FSEL_FB
FSELA
FSELB
FSELC
QA0-6
QB0-6
QC0-6
QFB
7
1
0
MPC9600
fref = 33.33 MHz
133.3 MHz
66.67 MHz
33.33 MHz (Feedback)
66.67 MHz
CCLK
FB_IN
FSEL_FB
FSELA
FSELB
FSELC
QA0-6
QB0-6
QC0-6
QFB
7
0
1
Power Supply Filtering
The MPC9600 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA (PLL) power supply impacts the device characteris-
tics, for instance I/O jitter. The MPC9600 provides separate
power supplies for the output buffers (VCC) and the phase-
locked loop (VCCA) of the device.The purpose of this design
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked loop.
In a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of isola-
tion may be required. The simple but effective form of isolation
is a power supply filter on the VCCA pin for the MPC9600. Fig-
ure 5 illustrates a typical power supply filter scheme. The
MPC9600 frequency and phase stability is most susceptible to
noise with spectral content in the 100kHz to 20MHz range.
Therefore the filter should be designed to target this range.
The key parameter that needs to be met in the final filter design
is the DC voltage drop across the series filter resistor RF. From
the data sheet the ICCA current (the current sourced through
the VCCA pin) is typically 3 mA (5 mA maximum), assuming
that a minimum of 2.325 V (VCC=3.3 V or VCC=2.5 V) must be
maintained on the VCCA pin. The resistor RF shown in Figure 5
“VCCA Power Supply Filter” must have a resistance of 9-10 W
(VCC=2.5 V) to meet the voltage drop criteria.
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 5 “VCCA Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
Figure 5. VCCA Power Supply Filter
VCCA
VCC
MPC9600
10 nF
RF = 9-10 for VCC = 2.5 V or VCC = 3.3 V
CF
33...100 nF
RF
VCC
CF = 22 F for VCC = 2.5 V or VCC = 3.3 V
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low im-
pedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9600 has several de-
sign features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be ade-
quate to eliminate power supply noise related problems in
most designs.
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9608ACR2 | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9608FAR2 | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9608AC | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC961CFAR2 | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC961CFA | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9608 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1:10 LVCMOS Zero Delay Clock Buffer |
| MPC9608AC | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9608ACR2 | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9608FA | 功能描述:時鐘緩沖器 3.3V 200MHz Clock Generator RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9608FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK BFFR SGL 32LQFP - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。