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參數(shù)資料
| 型號： | MPC952FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 97K |
| 代理商： | MPC952FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC952/D
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
168
Low Voltage PLL Clock Driver
The MPC952 is a 3.3V compatible, PLL based clock driver device tar-
geted for high performance clock tree applications. The device features a
fully integrated PLL with no external components required. With output
frequencies of up to 180MHz and eleven low skew outputs the MPC952 is
well suited for high performance designs. The device employs a fully dif-
ferential PLL design to optimize jitter and noise rejection performance.
Jitter is an increasingly important parameter as more microprocessors
and ASiC’s are employing on chip PLL clock distribution.
Fully Integrated PLL
Output Frequency up to 180MHz
High Impedance Disabled Outputs
Compatible with PowerPC, Intel and High Performance RISC Micro-
processors
Output Frequency Configurable
LQFP Packaging
±100ps Cycle–to–Cycle Jitter
The MPC952 features three banks of individually configurable outputs.
The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide
circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The
output frequency relationship is controlled by the fsel frequency control
pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL com-
patible inputs.
The MPC952 uses external feedback to the PLL. This features allows
for the use of the device as a “zero delay” buffer. Any of the eleven
outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL
stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test.
For system debug the PLL of the MPC952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
The outputs of the MPC952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
For applications using series terminated transmission lines each MPC952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
Rev 5
2
MPC952
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
See Upgrade Product – MPC9352
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC953 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC958 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9600 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER |
| MPC9600AE | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9600AER2 | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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