- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄29137 > MPC961PFA (FREESCALE SEMICONDUCTOR INC) 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC961PFA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | MPC961PFA |
492
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MPC961P
Rev 3, 08/2004
Low Voltage Zero Delay Buffer
The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay
buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the
device meets the needs of the most demanding clock tree applications.
Features
Fully Integrated PLL
Up to 200 MHz I/O Frequency
LVCMOS Outputs
Outputs Disable in High Impedance
LVPECL Reference Clock Options
LQFP Packaging
32-lead Pb-free Package Available
±50 ps Cycle-Cycle Jitter
150 ps Output Skews
Functional Description
The MPC961 is offered with two different input configurations. The
MPC961P offers an LVCMOS reference clock while the MPC961P offers an
LVPECL reference clock.
When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not
affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock.
The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS
compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50
transmission lines.
For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is
packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance.
Figure 1. MPC961P Logic Diagram
MPC961P
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
LOW VOLTAGE
ZERO DELAY BUFFER
PCLK
FB_IN
Q0
Q14
QFB
0
PLL
1
F_RANGE
OE
Q1
Q2
Q3
Q15
Q16
Ref
FB
100 – 200 MHz
50 – 100 MHz
The MPC961P requires an external RC filter for the analog power supply pin VCCA. Refer to APPLICATIONS INFORMATION for details.
50 k
PCLK
50 k
VCC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC962308D-4R2 | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962308D-2 | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962308D-5H | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962308D-3 | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| MPC962308D-3R2 | 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC962305 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305D-1 | 功能描述:IC CLOCK BUFFER 1:5 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC962305D-1H | 功能描述:IC CLOCK BUFFER 1:5 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC962305D-1HR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
| MPC962305D-1R2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。