參數(shù)資料
型號(hào)： MPC9352ACR2
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： LEAD FREE, LQFP-32
文件頁數(shù)： 5/16頁
文件大?。?/td> 346K
代理商： MPC9352ACR2
Advanced Clock Drivers Devices
Freescale Semiconductor
13
MPC9352
Figure 15. Propagation Delay (t(), static phase
offset) Test Reference
Figure 16. Output Duty Cycle (DC)
Figure 14. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
tSK(O)
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t()
CCLK
FB_IN
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
VCC
VCC ÷ 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 18. Cycle-to-Cycle Jitter
Figure 17. I/O Jitter
Figure 20. Output Transition Time Test Reference
tF
tR
VCC=3.3 V
VCC=2.5 V
2.4
1.8 V
0.55
0.6 V
TJIT() = |T0–T1mean|
CCLK
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
TJIT(PER) = |TN–1/f0|
T0
Figure 19. Period Jitter
相關(guān)PDF資料
PDF描述
MPC93H51FA PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93H51FAR2 PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93R52ACR2 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93R52AC 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC940FA MPC900 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9352FA 功能描述:鎖相環(huán) - PLL 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MPC9352FAR2 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel
MPC93H51AC 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC93H51ACR2 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC93H51FA 功能描述:IC PLL CLK DVR HI-DRIVE 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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