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參數(shù)資料
| 型號(hào)： | MPC9352ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 346K |
| 代理商： | MPC9352ACR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC9352
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency in PLL mode(2)
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
Input reference frequency in PLL bypass mode(3)
2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a
÷2 divider for feedback.
3. In PLL bypass mode, the MPC9352 divides the input reference clock.
50.0
33.3
25.0
16.67
100.0
66.6
50.0
33.3
250.0
MHz
fVCO
VCO lock frequency range(4)
4. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
200
400
MHz
fMAX
Output Frequency
÷2 output(5)
÷4 output
÷6 output
÷8 output
÷12 output
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay CCLK to FB_IN
fref > 40 MHz
(static phase offset)
fref < 40 MHz
–50
–200
+150
ps
PLL locked
tsk(O)
Output-to-output Skew(6)
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
6. See application section for part-to-part skew calculation.
200
100
ps
DC
Output duty cycle
47
50
53
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
8
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed
outputs are in any
÷4 and ÷6 combination
all outputs same frequency
400
250
100
ps
tJIT(PER) Period Jitter
output frequencies mixed
outputs are in any
÷4 and ÷6 combination
all outputs same frequency
200
150
75
ps
tJIT()
I/O Phase Jitter
÷4 feedback divider RMS (1 σ)(7)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
7. See application section for a jitter calculation for other confidence factors than 1
σ.
15
20
18 – 20
25
ps
BW
PLL closed loop bandwidth(8)
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
8. –3 dB point of PLL transfer characteristics.
3.0 – 10.0
1.5 – 6.0
1.0 – 3.5
0.5 – 2.0
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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