參數(shù)資料
型號(hào)： MPC9352ACR2
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9352 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： LEAD FREE, LQFP-32
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 346K
代理商： MPC9352ACR2
Advanced Clock Drivers Devices
Freescale Semiconductor
3
MPC9352
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
F_RANGE
Input
LVCMOS
PLL frequency range select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0–4, QB0–3, QC0–1 Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to
use an external RC filter for the analog power supply pin VCCA. Please see
applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2. Function Table
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 9 and Table 10 for supported frequency ranges and output to input frequency ratios.
F_RANGE
0
VCO
÷ 1 (High input frequency range)
VCO
÷ 2 (Low input frequency range)
FSELA
0
Output divider
÷ 4
Output divider
÷ 6
FSELB
0
Output divider
÷ 4
Output divider
÷ 2
FSELC
0
Output divider
÷ 2
Output divider
÷ 4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state) and reset of
the device. During reset, the PLL feedback loop is open
and the VCO is operating at its lowest frequency. The
MPC9352 requires reset at power-up and after any loss
of PLL lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length of the
reset pulse should be greater than two reference clock
cycles (CCLK).
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is substituted for
the internal VCO output. MPC9352 is fully static and no
minimum frequency limit applies. All PLL related AC
characteristics are not applicable.
相關(guān)PDF資料
PDF描述
MPC93H51FA PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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MPC93R52ACR2 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC93R52AC 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC940FA MPC900 SERIES, LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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參數(shù)描述
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MPC93H51FA 功能描述:IC PLL CLK DVR HI-DRIVE 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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