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參數資料
| 型號： | MPC932PFA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數： | 6/8頁 |
| 文件大?。?/td> | 115K |
| 代理商： | MPC932PFA |
MPC932P
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
6
Driving Transmission Lines
The MPC932P clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC932P clock driver. For
the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated
lines. Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC932P clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 4. Single versus Dual Transmission Lines
7
IN
MPC932P
OUTPUT
BUFFER
RS = 43
ZO = 50
OutA
7
IN
MPC932P
OUTPUT
BUFFER
RS = 43
ZO = 50
OutB0
RS = 43
ZO = 50
OutB1
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC932P output buffers is
more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC932P. The output
waveform in Figure 5 shows a step in the waveform, this step
is caused by the impedance mismatch seen looking into the
driver. The parallel combination of the 43
series resistor
plus the output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50
|| 50
Rs = 43
|| 43
Ro = 7
VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)
= 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Figure 5. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 6. Optimized Dual Line Termination
7
MPC932P
OUTPUT
BUFFER
RS = 36
ZO = 50
RS = 36
ZO = 50
7
+ 36 k 36 = 50 k 50
25
= 25
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
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