- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26838 > MPC9315ACR2 (INTEGRATED DEVICE TECHNOLOGY INC) 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC9315ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 401K |
| 代理商： | MPC9315ACR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
9
MPC9315
Using the MPC9315 in Zero-Delay Applications
The external feedback option of the MPC9315 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the
MPC9315 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Calculation of Part-to-Part Skew
The MPC9315 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9315 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Due to the statistical nature of I/O jitter, an RMS value (1
σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 12.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (
± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –300 ps to +300 ps relative to TCLK (VCC =3.3 V
VCO = 160 MHz):
tSK(PP) = [–150ps...150ps] + [–150ps...150ps] +
[(10ps @ –3)...(10ps @ 3)] + tPD, LINE(FB)
tSK(PP) = [–300ps...300ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC =3.3 V (10 ps
RMS). I/O jitter is frequency-dependant with a maximum at
the lowest VCO frequency (160 MHz for the MPC9315).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and for
part-to-part skew tSK(PP).
Table 12. Confidence Factor CF
CF
Probability of Clock Edge within the Distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
Figure 7. MPC9315 max. Device-to-Device Skew
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
TCLKCOMMON
Figure 8. Max. I/O Jitter (RMS) versus frequency for VCC
= 2.5 V
30
25
20
15
10
5
0
75
100
125
150
175
200
VCO frequency [MHz]
t JI
T(
)[p
s]
ms
I/O Jitter (RMS) versus VCO frequency
Figure 9. Max. I/O Jitter (RMS) versus frequency for VCC
= 3.3 V
30
25
20
15
10
5
0
75
100
125
150
175
200
t JI
T(
)
[p
s]
ms
I/O Jitter (RMS) versus VCO frequency
VCO frequency (MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC932FAR2 | MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC932FA | 932 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC932PFA | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9331FA | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9331FAR2 | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9315FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9330 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。