參數(shù)資料
型號(hào)： MPC9315ACR2
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32
文件頁(yè)數(shù)： 14/16頁(yè)
文件大小： 401K
代理商： MPC9315ACR2
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC9315
APPLICATIONS INFORMATION
Programming the MPC9315
The PLL of the MPC9315 supports output clock
frequencies from 18.75 to 160 MHz. Different feedback and
output divider configurations can be used to achieve the
desired input to output frequency relationship. The feedback
frequency and divider should be used to situate the VCO in
the frequency range between 75 and 160 MHz for stable and
optimal operation. The FSELA, FSELB, FSELC pins select
the desired output clock frequencies. Possible frequency
ratios of the reference clock input to the outputs are 1:1, 1:2,
1:4 as well as 2:1 and 4:1, Table 9, Table 10, and Table 11
illustrate the various output configurations and frequency
ratios supported by the MPC9315. PSELA controls the output
phase of the QA0 and QA1 outputs, allowing the user to
generate inverted clock signals synchronous to non-inverted
clock signals. See also Example Configurations for the
MPC9315 for further reference.
Table 9. Output Frequency Relationship for QA0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
÷ 2
0
1
CLK
÷ 4
0
1
0
CLK
÷ 2
CLK
÷ 2
0
1
CLK
÷ 2
CLK
÷ 4
1
0
CLK
2 * CLK
CLK
1
0
1
CLK
2 * CLK
CLK
÷ 2
1
0
CLK
1
CLK
÷ 2
Table 10. Output Frequency Relationship for QB0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
CLK
÷ 2
0
1
CLK
÷ 4
0
1
0
2 * CLK
CLK
0
1
2 * CLK
CLK
÷ 2
1
0
CLK
÷ 2
CLK
÷ 2
1
0
1
CLK
÷ 2
CLK
÷ 4
1
0
CLK
1
CLK
÷ 2
Table 11. Output Frequency Relationship for QC0 connected to FB0(1)
1. Output frequency relationship with respect to input reference frequency CLK.
Inputs
Outputs
FSELA
FSELB
FSELC
QA0, QA1
QB0–QB3
QC0, QC1
0
2 * CLK
CLK
0
1
4 * CLK
CLK
0
1
0
2 * CLK
CLK
0
1
4 * CLK
2 * CLK
CLK
1
0
CLK
2 * CLK
CLK
1
0
1
2 * CLK
4 * CLK
CLK
1
0
CLK
1
2 * CLK
CLK
相關(guān)PDF資料
PDF描述
MPC932FAR2 MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC932FA 932 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC932PFA PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9331FA PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
MPC9331FAR2 PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC9315FA 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MPC9315FAR2 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R
MPC931FA 制造商:Motorola Inc 功能描述:
MPC932 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER
MPC9330 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*