- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26838 > MPC9315ACR2 (INTEGRATED DEVICE TECHNOLOGY INC) 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MPC9315ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 401K |
| 代理商： | MPC9315ACR2 |
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC9315
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40° to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
÷1 feedback
÷2 feedback
÷4 feedback
PLL bypass mode
100(2)
37.50
18.75
0
2. The VCO range in
÷1 feedback configuration (e.g. QAx connected to FBx and FSELA = 0) is limited to 100 ≤ fVCO ≤ 160 MHz. Please see
next revision of the MPC9315 for improved VCO frequency range.
160
80
40
TBD
MHz
PLL locked
VCCA = GND
fVCO
VCO Lock Range
75(2)
160
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2 output
÷4 output
75
37.50
18.75
160
80
40
MHz
frefDC
Reference Input Duty Cycle
25
75
%
tr, tf
CLK0, CLK1 Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay
CLK0 or CLK1 to FB
(Static Phase Offset)
-150
+150
ps
PLL locked
tSK()
Output-to-Output Skew
Within one bank
Any output
80
120
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
BW
PLL closed loop bandwidth
÷1 feedback
÷2 feedback
÷4 feedback
TBD
2.0 - 20
0.6 - 6.0
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
(1
σ)
10
22
ps
RMS value
tJIT(PER) Period Jitter
(1
σ)
8.0
15
ps
RMS value
tJIT()
I/O Phase Jitter
(1
σ)
8.0 - 25(3)
3. I/O jitter depends on VCO frequency. Please see application section for I/O jitter versus VCO frequency characteristics.
TBD
ps
RMS value
tLOCK
Maximum PLL Lock Time
1.0
ms
Table 7. DC Characteristics (VCC = 2.5 V ± 5%, TA = -40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH = –15 mA(1)
1. The MPC9315 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
VOL
Output Low Voltage
0.6
V
IOL= 15 mA
ZOUT
Output Impedance
17 - 20
IIN
Input Current(2)
2. Inputs have pull-up or pull-down resistors affecting the input current.
±200
A
VIN = VCC or
GND
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICCQ
Maximum Quiescent Supply Current
1.0
mA
All VCC Pins
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC932FAR2 | MPC900 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC932FA | 932 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC932PFA | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9331FA | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9331FAR2 | PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9315FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9330 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。