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參數(shù)資料
| 型號： | MPC92433FA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 1428 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 820K |
| 代理商： | MPC92433FA |
IDT / ICS DUAL LVPECL CLOCK SYNTHESIZER
9
MPC92433 REV. 3 NOVEMBER 10, 2008
MPC92433
1428MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
PLL Divider Configuration
Programming the MPC92433
The MPC92433 has a parallel and a serial configuration
interface. The purpose of the parallel interface is to directly
configure the PLL dividers through hardware pins without the
overhead of a serial protocol. At device startup, the device always
obtains an initial PLL frequency configuration through the parallel
interface. The parallel interface does not support reading the PLL
configuration.
The serial interface is I2C compatible. It allows reading and
writing devices settings by accessing internal device registers.
The serial interface is designed for host-controller access to the
synthesizer frequency settings for instance in frequency-
margining applications.
Using the Parallel Interface
The parallel interface supports write-access to the PLL
frequency setting directly through 15 configuration pins (P, M[9:0],
NA[2:0], and NB). The parallel interface must be enabled by
setting PLOAD to logic low level. During PLOAD = 0, any change
of the logical state of the P, M[9:0], NA[2:0], and NB pins will
immediately affect the internal PLL divider settings, resulting in a
change of the internal VCO-frequency and the output frequency.
The parallel interface mode disables the I2C write-access to the
internal registers; however, I2C read-access to the internal
configuration registers is enabled.
Upon startup, when the device reset signal is released (rising
edge of the MR signal), the device reads its startup configuration
through the parallel interface and independent on the state of
PLOAD. It is recommended to provide a valid PLL configuration
for startup. If the parallel interface pins are left open, a default PLL
configuration will be loaded. After the low-to-high transition of
PLOAD, the configuration pins have no more effect and the
configuration registers are made accessible through the serial
interface.
Using the I2C Interface
PLOAD = 1 enables the programming and monitoring of the
internal registers through the I2C interface. Device register access
(write and read) is possible through the 2-wire interface using
SDA (configuration data) and SCL (configuration clock) signals.
The MPC92433 acts as a slave device at the I2C bus. For further
information on I2C it is recommended to refer to the I2C bus
specification (version 2.1).
PLOAD = 0 disables the I2C-write-access to the configuration
registers and any data written into the register is ignored. Howev-
er, the MPC92433 is still visible at the I2C interface and I2C trans-
fers are acknowledged by the device. Read-access to the internal
registers during PLOAD = 0 (parallel programming mode) is sup-
ported.
Note that the device automatically obtains a configuration using
the parallel interface upon the release of the device reset (rising
edge of MR) and independent on the state of PLOAD. Changing
the state of the PLOAD input is not supported when the device
performs any transactions on the I2C interface.
Programming Model and Register Set
The synthesizer contains two fully accessible configuration
registers (PLL_L and PLL_H) and a write-only command register
(CMD). Programming the synthesizer frequency through the I2C
interface requires two steps: 1) writing a valid PLL configuration to
the configuration registers and 2) loading the registers into the
PLL by an I2C command. The PLL frequency is affected as a
result of the second step.
This two-step procedure can be performed by a single I2C
transaction or by multiple, independent I2C transactions. An
alternative way to achieve small PLL frequency changes is to use
the increment or decrement commands of the synthesizer, which
have an immediate effect on the PLL frequency.
Table 8. Pre-PLL Divider P
PValue
0fREF ÷ 2
1fREF ÷ 4
Table 9. Post-PLL Divider NA and NB
NA2
NA1
NA0
NB
fOUT (QA)
fOUT (QB)
00
0
fVCO ÷ 2
00
1
0
fVCO ÷ 32
01
0
fVCO ÷ 8
01
1
0
fVCO ÷ 12
10
0
fVCO ÷ 4
10
1
0
fVCO ÷ 6
11
0
fVCO ÷ 16
11
1
0n/a
n/a
00
0
1
fVCO ÷ 2
fVCO ÷ 4
00
1
1n/a
n/a
01
0
1
fVCO ÷ 8
fVCO ÷ 16
01
1
1n/a
n/a
10
0
1
fVCO ÷ 4
fVCO ÷ 8
10
1
fVCO ÷ 6
fVCO ÷ 12
11
0
1
fVCO ÷ 16
fVCO ÷ 32
11
1
1n/a
n/a
Table 10. Feedback Divider Configuration
Feedback
Divider M
987654321
0
Pin
M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
Default
011111010
0
Table 11. PLL Pre/Post Divider Configuration (N, P)
Post-D.
NA
21
0
Post-D.
NB
NB
Pre-D.
P
P
Pin
NA2
NA1
NA0
Pin
NB
Pin
P
Default
01
0
Default
0
Default
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439EI | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439EIR2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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