參數(shù)資料
型號: MPC92433FA
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 1428 MHz, OTHER CLOCK GENERATOR, PQFP48
封裝: LQFP-48
文件頁數(shù): 18/20頁
文件大?。?/td> 820K
代理商: MPC92433FA
IDT / ICS DUAL LVPECL CLOCK SYNTHESIZER
7
MPC92433 REV. 3 NOVEMBER 10, 2008
MPC92433
1428MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TJ = –40°C to +85°C(1) (2)
1. AC specifications are subject to change.
2. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
15
16
20
MHz
fREF
FREF_EXT Reference Frequency Range
15
20
MHz
fVCO
VCO Frequency Range(3)
3. The input frequency fXTAL, the PLL divider M and P must match the VCO frequency range: fVCO = fXTAL M ÷ P. The feedback divider M is
limited to 170 <= M <= 357 (for P=2) and 340 <= M <= 714 (for P=4) for stable PLL operation.
1360
2856
MHz
fMAX
Output Frequency(4)
N= ÷2
N= ÷4
N= ÷6
N= ÷8
N= ÷12
N= ÷16
N= ÷32
4. Output frequency for QA, QB if NB=0. With NB=1 the QB output frequency is half of the QA output frequency.
680
340
226.67
170
113.30
85
42.50
1428
714
476
357
238
178.50
89.25
MHz
fSCL
Serial Interface (I2C) Clock Frequency
0
0.4
MHz
tP,MIN
Minimum Pulse Width
(P_LOAD)50
ns
DC
Output Duty Cycle
45
50
55
%
tSK(O)
Output-to-Output Skew
NB=0 (fQA = fQB)
NB=1 (fQA = 2 fQB)
38
96
ps
tr, tf
Output Rise/Fall Time (QA, QB)
0.05
0.3
ns
20% to 80%
tr, tf
Output Rise/Fall Time (SDA)
250
ns
CL = 400 pF
tP_EN
Output Enable Time (CLKSTOPx to QA, QB)
0
2 TQx
TQx = Output period
tP_DIS
Output Disable Time (CLKSTOPx to QA, QB)
0
1.5 TQx
TQx = Output period
tJIT(CC)
Cycle-to-Cycle Jitter (RMS)(5) N= ÷2, ÷4, ÷6, ÷8
N= ÷12
N= ÷16, ÷32
5. Maximum cycle jitter measured at the lowest VCO frequency. Refer to Figure 8 for the cycle jitter vs. frequency characterisitics.
15
20
30
ps
tJIT(PER)
Period Jitter (RMS)(6)
N= ÷2
N= ÷4
N= ÷6
N= ÷8
N= ÷12
N= ÷16
N= ÷32
6. Maximum period jitter measured at the lowest VCO frequency. Refer to Figure 9 for the period jitter vs. frequency characterisitics.
8
10
12
13
17
23
29
ps
NREF(UNLOCK) Number of missing reference clock cycles to
declare an out of LOCK condition(7)
7. See the LOCK Detect section on page 13.
2
tLOCK
Maximum PLL Lock Time
10
ms
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