參數(shù)資料
型號: MPC8544EDVTANG
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
封裝: 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁數(shù): 63/128頁
文件大?。?/td> 1411K
代理商: MPC8544EDVTANG
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
4
Freescale Semiconductor
MPC8544E Overview
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports a variety of other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, WTLS/WAP, SSL/TLS, and 3GPP
— Four crypto-channels, each supporting multi-command descriptor chains
Dynamic assignment of crypto-execution units via an integrated controller
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— PKEU—public key execution unit
– RSA and Diffie-Hellman; programmable field size up to 2048 bits
– Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to
511 bits
— DEU—Data Encryption Standard execution unit
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— AESU—Advanced Encryption Standard unit
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, and CCM modes
– 128-, 192-, and 256-bit key lengths
— AFEU—ARC four execution unit
Implements a stream cipher compatible with the RC4 algorithm
40- to 128-bit programmable key
— MDEU—message digest execution unit
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— KEU—Kasumi execution unit
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA-3 algorithms
— RNG—random number generator
— XOR engine for parity checking in RAID storage applications
Dual I2C controllers
相關(guān)PDF資料
PDF描述
MPC8544AVTANG 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
MPC8544AVTAQG 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
MPC8544EAVTAQG 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
MPC8544EVTANG 32-BIT, 800 MHz, MICROPROCESSOR, PBGA783
MPC8544ECVTARJ 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA783
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