參數(shù)資料
型號： MPC8544EDVTANG
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FC-PBGA-783
文件頁數(shù)： 36/128頁
文件大?。?/td> 1411K
代理商： MPC8544EDVTANG
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
15
Input Clocks
4
Input Clocks
4.1
System Clock Timing
Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8544E.
4.1.1
SYSCLK and Spread Spectrum Sources
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference emissions
(EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise magnitude in order to meet
industry and government requirements. These clock sources intentionally add long-term jitter in order to diffuse the
EMI spectral content. The jitter specification given in Table 6 considers short-term (cycle-to-cycle) jitter only and
the clock generator’s cycle-to-cycle output jitter should meet the MPC8544E input cycle-to-cycle jitter requirement.
Frequency modulation and spread are separate concerns, and the MPC8544E is compatible with spread spectrum
sources if the recommendations listed in Table 7 are observed.
Table 6. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
SYSCLK frequency
fSYSCLK
33
—
133
MHz
1
SYSCLK cycle time
tSYSCLK
7.5
—
30.3
ns
—
SYSCLK rise and fall time
tKH, tKL
0.6
1.0
2.1
ns
2
SYSCLK duty cycle
tKHK/tSYSCLK
40
—
60
%
—
SYSCLK jitter
—
±150
ps
3, 4
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” and Section 19.3, “e500 Core PLL Ratio,” for ratio
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. This represents the total input jitter—short- and long-term.
4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
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