參數(shù)資料
型號： MPC8544CVTAQJB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 89/120頁
文件大小： 1321K
代理商： MPC8544CVTAQJB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
70
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
16.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are HCSL
(high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be
used but may need to be AC-coupled due to the limited common mode input range allowed (100 to
400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock
driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to
AC-coupling.
NOTE
Figure 49 through Figure 52 are for conceptual reference only. Due to the
fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8544E SerDes reference clock receiver requirement
provided in this document.
Figure 49 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8544E SerDes reference clock
input’s DC requirement.
Figure 49. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
CLK_Out
MPC8544E
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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