參數(shù)資料
型號： MPC8544CVTAQJB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-783
文件頁數(shù)： 51/120頁
文件大小： 1321K
代理商： MPC8544CVTAQJB
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
36
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 18 shows the MII receive AC timing diagram.
Figure 18. MII Receive AC Timing Diagram
8.7
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.7.1
TBI Transmit AC Timing Specifications
Table 34 provides the TBI transmit AC timing specifications.
Table 34. TBI Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5V ± 5%..
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
GTX_CLK clock period
tGTX
—8.0
—
ns
—
GTX_CLK to TCG[9:0] delay time
tTTKHDX
0.2
—
5.0
ns
2
GTX_CLK rise (20%–80%)
tTTXR
——
1.0
ns
—
GTX_CLK fall time (80%–20%)
tTTXF
——
1.0
ns
—
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going
high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. Data valid tTTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time –
Max delay).
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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