參數(shù)資料
型號(hào)： MPC853TZT66A
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 12/88頁(yè)
文件大小： 0K
描述： IC MPU PWRQUICC 66MHZ 256-PBGA
標(biāo)準(zhǔn)包裝： 60
系列： MPC8xx
處理器類(lèi)型： 32-位 MPC8xx PowerQUICC
速度： 66MHz
電壓： 1.8V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（23x23）
包裝： 托盤(pán)
MPC853T Hardware Specification, Rev. 1
2
Freescale Semiconductor
Features
and incorporates memory management units (MMUs), instruction and data caches. The MPC853T is a subset of this
family of devices and is the main focus of this document.
2Features
The MPC853T is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM). The MPC853T block diagram is shown in
The following list summarizes the key MPC853T features:
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— The 50-/66-MHz core frequencies support both the 1:1 and 2:1 modes.
— The 80-/100-MHz core frequencies support 2:1 mode only.
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch and without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
– Instruction cache is two-way, set-associative with 128 sets
– Data cache is two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
are lockable on a cache block basis.
— MMUs with 32-entry translation look-aside buffer (TLB), fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 512 Kbytes, and 8 Mbytes; 16 virtual
address spaces and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank.
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
Fast Ethernet Controller (FEC)
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