參數(shù)資料
型號： MPC8536E-ANDROID
廠商： Freescale Semiconductor
文件頁數(shù)： 52/126頁
文件大?。?/td> 0K
描述： HARDWARE/SOFTWARE ANDROID OS
標準包裝： 1
系列： PowerQUICC ™
類型： MPU
適用于相關(guān)產(chǎn)品： MPC8536
所含物品： 板
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
31
2.4.6
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed. The “platform clock (CCB) frequency”
in the following formula refers to the maximum platform (CCB) frequency of the speed bins the part belongs to, which is
defined in Table 73.
For FIFO GMII mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than 167 MHz
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more than
167 MHz
2.4.7
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific
section of this document.
2.5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of the chip. This table
provides the RESET initialization AC timing specifications for the DDR SDRAM component(s).
This table provides the PLL lock times.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HREST
100
—
μs—
Minimum assertion time for SRESET
3—
Sysclk
1
PLL input setup time with stable SYSCLK before HRESET negation
100
—
μs—
Input setup time for POR configurations (other than PLL config) with respect to negation of
HRESET
4
—
SYSCLKs
1
Input hold time for all POR configurations (including PLL config) with respect to negation of
HRESET
2
—
SYSCLKs
1
Maximum valid-to-high impedance time for actively driven POR configurations with respect to
negation of HRESET
—
5
SYSCLKs
1
HRESET rise time
—
1
SYSCLK
—
Notes:
1. SYSCLK is the primary clock input for the chip.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
—
100
μs—
Local bus PLL
—
50
μs—
PCI bus lock time
—
50
μs—
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