參數(shù)資料
型號: MPC8536E-ANDROID
廠商: Freescale Semiconductor
文件頁數(shù): 6/126頁
文件大?。?/td> 0K
描述: HARDWARE/SOFTWARE ANDROID OS
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC ™
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8536
所含物品:
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
103
2.21.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of
any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter
median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the
transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
It is recommended that the recovered TX UI is calculated using all edges in the 3500
consecutive UI interval with a fit algorithm using a minimization merit function (that is,
least squares and median deviation fits).
Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
[De-Emphasized Bit]
0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)
566 mV (3 dB ) >=
VTX-DIFFp-p-MIN >= 505 mV (4 dB )
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
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