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參數(shù)資料
型號： MPC8533VTARJA
廠商： Freescale Semiconductor
文件頁數(shù)： 7/112頁
文件大?。?/td> 0K
描述： MPU POWERQUICC 783-PBGA
標準包裝： 36
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.067GHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
104
Freescale Semiconductor
System Design Information
resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then,
Z0 =(RP +RN) 2.
Figure 63. Driver Impedance Measurement
Table 68 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,
nominal OVDD, 90C.
21.8
Configuration Pin Muxing
The MPC8533E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k
on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 k
. This value should permit the 4.7-kresistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
Table 68. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART,
Control, Configuration, Power
Management
PCI
DDR DRAM
Symbol
Unit
RN
43 Target
25 Target
20 Target
Z0
W
RP
43 Target
25 Target
20 Target
Z0
W
Note: Nominal supply voltages. See Table 1.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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