參數(shù)資料
型號(hào)： MPC8533VTARJA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/112頁(yè)
文件大小： 0K
描述： MPU POWERQUICC 783-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.067GHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
103
System Design Information
21.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to VDD, TVDD, BVDD, OVDD, GVDD, and LVDD as
required. All unused active high inputs should be connected to GND. All NC (no connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD, TVDD, BVDD,
OVDD, GVDD, and LVDD, and GND pins of the device.
21.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8533E requires weak pull-up resistors (2–10 k
is recommended) on open drain type pins
including I2C pins and MPIC interrupt pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 65. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL pins
must be set to a proper state during POR configuration. Refer to the pinout listing table (Table 57) for more
details. Refer to the PCI 2.2 Local Bus Specifications, for all pullups required for PCI.
21.7
Output Buffer DC Impedance
The MPC8533E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers,
an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is
varied until the pad voltage is OVDD/2 (see Figure 63). The output impedance is the average of two
components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed
(SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the
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