參數(shù)資料
型號(hào): MPC8377EWLANB
廠商: Freescale Semiconductor
文件頁數(shù): 113/127頁
文件大?。?/td> 0K
描述: ACCESS POINT/ROUTER MPC8377
標(biāo)準(zhǔn)包裝: 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
86
Freescale Semiconductor
driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock
driver chip.
Figure 58. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
Figure 59. Single-Ended Connection (Reference Only)
21.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK Driver Chip
R2
R1
10 nF
Chip
50
Ω
50
Ω
SD
n_REF_CLK
SD
n_REF_CLK
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
50
Ω
Chip
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