參數(shù)資料
型號: MPC8377EWLANB
廠商: Freescale Semiconductor
文件頁數(shù): 110/127頁
文件大?。?/td> 0K
描述: ACCESS POINT/ROUTER MPC8377
標(biāo)準(zhǔn)包裝: 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
83
Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 55. Single-Ended Reference Clock Input DC Requirements
21.2.3
Interfacing With Other Differential Signaling Levels
The following list provides information about interfacing with other differential signaling levels.
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed
(100 mV to 400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
SD
n_REF_CLK
SD
n_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
150
Vmin > Vcm – 400m V
fdafdVmax < Vcm + 400 mV
Vmax < Vcm + 400 mV
SD
n_REF_CLK
SD
n_REF_CLK
400 mV < SD
n_REF_CLK Input Amplitude < 800 mV
0V
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