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參數(shù)資料
| 型號(hào)： | MPC8360EZUALFHA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 54/102頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II PRO 740TBGA |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 667MHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 740-LBGA |
| 供應(yīng)商設(shè)備封裝： | 740-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 配用： | MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC |
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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
55
SPI AC Timing Specifications
This figure provides the AC test load for the SPI.
Figure 41. SPI AC Test Load
These figures represent the AC timing from Table 56. Note that although the specifications generally reference the rising edge
of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
This figure shows the SPI timing in slave mode (external clock).
Figure 42. SPI AC Timing in Slave Mode (External Clock) Diagram
This figure shows the SPI timing in Master mode (internal clock).
Figure 43. SPI AC Timing in Master Mode (Internal Clock) Diagram
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI
outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are
valid (V).
Table 56. SPI AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
SPICLK (Input)
tNEIXKH
tNEIVKH
tNEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (Output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH
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