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| 型號： | MPC8360EZUALFHA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 27/102頁 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II PRO 740TBGA |
| 標準包裝： | 21 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 667MHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 740-LBGA |
| 供應商設備封裝： | 740-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 配用： | MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC |
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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
30
Freescale Semiconductor
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.2.2
MII Receive AC Timing Specifications
This table provides the MII receive AC timing specifications.
This figure provides the AC test load.
Figure 13. AC Test Load
This figure shows the MII receive AC timing diagram.
Figure 14. MII Receive AC Timing Diagram
Table 30. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—40—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
ns
RX_CLK clock rise time, (20% to 80%)
tMRXR
1.0
—
4.0
ns
RX_CLK clock fall time, (80% to 20%)
tMRXF
1.0
—
4.0
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)
going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
Output
Z0 = 50 Ω
LVDD/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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相關代理商/技術參數(shù) |
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|---|---|
| MPC8360TVVAGDGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360TVVAGDHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360TVVAGFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360TVVAGFHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360TVVAHFG | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC⑩ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
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