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參數(shù)資料
| 型號： | MPC8360EVVAJDGA |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC II PRO 740TBGA |
| 標(biāo)準(zhǔn)包裝： | 21 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 533MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 740-LBGA |
| 供應(yīng)商設(shè)備封裝： | 740-TBGA（37.5x37.5） |
| 包裝： | 托盤 |
| 配用： | MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC |
MPC8360E PowerQUICC II Pro Processor Product Brief, Rev. 0
2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Overview
the MPC8360E. The QUICC Engine contains several peripheral controllers and integrates two 32-bit
RISC controllers. Each RISC controller can control multiple peripherals and they work together to provide
increased aggregated system bandwidth for higher throughput applications. Protocol support is provided
by the main workhorses of the device—the unified communication controllers (UCCs) and multi-channel
communication controller (MCC). A block diagram of the MPC8360E is shown in Figure 1.
Figure 1. MPC8360E Block Diagram
Each of the eight UCCs can support a variety of communication protocols: 10/100/1000 Mbps Ethernet
GMII/RGMII/TBI/RTBI, ATM/POS PHY support up to OC-12 speeds, serial ATM, multi-PHY ATM,
HDLC, UART, and BISYNC. The MCC is capable of supporting up to 256 TDM channels in either
transparent or HDLC modes, and multi-link/class PPP. Inverse multiplexing over ATM is supported and
allows ATM traffic to be distributed across multiple E1/T1 circuits.
In addition, the QUICC Engine can also support two UTOPIA level 2 or two POS interfaces, each interface
capable of supporting 124 multi-PHY, or up to two, 128 multi-PHY interfaces using extended address
mode. The QUICC Engine also features an integrated 8-port, L2 Ethernet switch which can provide four
priority levels on each port, VLAN functionality, IGMP snooping, network auto-negotiation functions,
store-and-forward switching and packet-error filtering. Enhanced interworking features within the QUICC
Memory Controllers
GPCM/UPM/SDRAM
32/64 DDR Interface Unit
PCI Bridge
Local Bus
Bus Arbitration
DUART
Dual I2C
4 Channel DMA
Interrupt Controller
Protection & Configuration
System Reset
Clock Synthesizer
System Interface Unit
(SIU)
Local
Baud Rate
Generators
Parallel I/O
Accelerators
Dual 32-bit RISC CP
2 GMII/
RGMII/TBI/RTBI
8 MII/
RMII
8 TDM Ports
2 UL2/POS
(124 MPHY)
QUICC Engine
JTAG/COP
Power
Management
Timers
FPU
Classic G2 MMUs
32KB
D-Cache
32KB
I-Cache
Security Engine
e300 Core
PCI
DDR
MPC8360E
UCC4
UCC3
UCC2
UCC1
MCC
Multi-User
RAM
Serial DMA
&
2 Virtual
DMAs
Serial Interface
UCC8
UCC7
UCC6
UCC5
SPI
USB
Time Slot Assigner
SPI
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8360EVVAJDHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360EVVAJFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360EVVAJFHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360EVVALDGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360EVVALDHA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
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