參數(shù)資料
型號(hào): MPC8360EA-MDS-PB
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 59/102頁(yè)
文件大?。?/td> 0K
描述: KIT APPLICATION DEV 8360 SYSTEM
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8360EA
所含物品:
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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
6
Freescale Semiconductor
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers, both support ECC)
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
PCI interface
— PCI Specification Revision 2.3 compatible
— Data bus widths:
Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target
— Internal configuration registers accessible from PCI
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
General-purpose chip select machine (GPCM)
Three user programmable machines (UPMs)
Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
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MPC8360ECVVAGDHA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications
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