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| 型號(hào)： | MPC8360E-MDS-PBE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD PROCESSOR FOR MPC8360E |
| 標(biāo)準(zhǔn)包裝： | 1 |
MPC8360E PowerQUICC II Pro Processor Product Brief, Rev. 0
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
Architecture Overview
Seamless connection to PowerQUICC III family devices for increased control (CPU) application
processing requirements
3.1.1
Protocols
ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for up to
64K ATM connections
Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0)
Support for IMA and ATM transmission convergence sub-layer
ATM OAM handling features compatible with ITU-T I.610
PPP, multi-link (ML-PPP), multi-class (MC-PPP) and PPP multiplexing in accordance with the
following RFCs: 1661, 1662, 1990, 2686 and 3153
IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum
processing
L2 Ethernet switching using MAC address or IEEE 802.1P/Q VLAN tags
Support for ATM (AAL2/AAL5) to Ethernet (IP) interworking
Extensive support for ATM statistics and Ethernet RMON/MIB statistics.
Support for 256 channels or HDLC/transparent or 128 channels of SS#7
3.1.2
Serial Interfaces
Support for two UL2 / POS-PHY interfaces with 124 multi-PHY addresses each.
Support for two 1000Mbps Ethernet interfaces using GMII or RGMII, TBI, RTBI.
Support for up to eight 10/100Mbps Ethernet interfaces using MII or RMII
Support for up to eight T1/E1/J1/E3 or DS-3 serial interfaces
Support for dual UART, I2C and SPI interfaces.
System scalability is also made available through the number of UCCs and MCCs. The initial
implementation offers eight UCCs and one MCC; however as a result of the system-on-a-chip design
methodology used for the QUICC Engine, these numbers can be scaled to support an optimized mix of
communications channels. The flexible architecture of the QUICC Engine allows customers to customize
their own application protocol and filtering requirements, allowing Freescale to add more RISC engines
and/or UCCs on future family derivatives.
3.2
QUICC Engine
The QUICC Engine is a versatile communications complex that integrates several communications
peripheral controllers. It provides on-chip system design for a variety of applications, particularly in
communications and networking systems. The QUICC Engine has the following features:
Two 32-bit RISC controllers for flexible support of the communications peripherals
Serial DMA channel for receive and transmit on all serial channels
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