參數(shù)資料
型號(hào): MPC8358ECVRAGDGA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 77/95頁(yè)
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 668-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
79
Clocking
NOTE
Core VCO frequency = Core frequency × VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO
frequency is in the range of 800–1800 MHz. Having a core frequency below
the CSB frequency is not a possible option because the core frequency must
be equal to or greater than the CSB frequency.
22.3
QUICC Engine Block PLL Configuration
The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and
RCWL[CEVCOD] parameters. Table 72 shows the multiplication factor encodings for the QUICC Engine
block PLL.
11
0001
11.5:1
÷8
00
0010
02:1
÷2
01
0010
02:1
÷4
10
0010
02:1
÷8
11
0010
02:1
÷8
00
0010
12.5:1
÷2
01
0010
12.5:1
÷4
10
0010
12.5:1
÷8
11
0010
12.5:1
÷8
00
0011
03:1
÷2
01
0011
03:1
÷4
10
0011
03:1
÷8
11
0011
03:1
÷8
Table 72. QUICC Engine Block PLL Multiplication Factors
RCWL[CEPMF] RCWL[CEPDF]
QUICC Engine PLL
Multiplication Factor = RCWL[CEPMF]/
(1 + RCWL[CEPDF])
00000
0
× 16
00001
0
Reserved
00010
0
× 2
00011
0
× 3
00100
0
× 4
Table 71. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk:csb_clk
Ratio
VCO divider
0–1
2–5
6
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MPC8358ECVVADDEA 功能描述:微處理器 - MPU 8360 TBGA C ENC NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8358ECVVADDGA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MPC8360E/MPC8358E PowerQUICC II Pro Processor
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