參數(shù)資料
型號(hào)： MPC8323CZQAFDC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 41/82頁(yè)
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤(pán)
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
46
Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
Figure 38 provides the AC test load.
Figure 38. AC Test Load
Figure 39 and Figure 40 represent the AC timing from Table 51. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Inputs—External clock input hold time
tHEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 52. Synchronous UART AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tUAIKHOV
05.5
ns
Outputs—External clock delay
tUAEKHOV
110
ns
Outputs—Internal clock high impedance
tUAIKHOX
05.5
ns
Outputs—External clock high impedance
tUAEKHOX
18
ns
Inputs—Internal clock input setup time
tUAIIVKH
6—
ns
Inputs—External clock input setup time
tUAEIVKH
4—
ns
Inputs—Internal clock input hold time
tUAIIXKH
0—
ns
Inputs—External clock input hold time
tUAEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUAIKHOX symbolizes the outputs
internal timing (UAI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1 (continued)
Characteristic
Symbol2
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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