參數(shù)資料
型號(hào)： MPC8308CVMAFD
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 77/83頁(yè)
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 473MAPBGA
產(chǎn)品培訓(xùn)模塊： MPC8308 PowerQUICC II Pro Processor
特色產(chǎn)品： MPC8308 PowerQUICC? II Pro Processor
標(biāo)準(zhǔn)包裝： 84
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 473-LFBGA
供應(yīng)商設(shè)備封裝： 473-MAPBGA（19x19）
包裝： 托盤
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor
79
System Design Information
Figure 55. Driver Impedance Measurement
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V1 = Rsource Isource. Second, the output voltage is measured
while driving logic 1 with an external precision differential termination resistor of value Rterm. The
measured voltage is V2 =(1/(1/R1 +1/R2)) Isource. Solving for the output impedance gives Rsource =
Rterm (V1/V2 – 1). The drive current is then Isource =V1/Rsource.
This table summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal NVDD, 105C.
23.6
Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 K
on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While PORESET is asserted however, these pins are treated as inputs. The value presented on these pins
while PORESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
Table 60. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART, Control,
Configuration, Power Management
DDR DRAM
Symbol
Unit
RN
42 Target
20 Target
Z0
RP
42 Target
20 Target
Z0
Note: Nominal supply voltages. See Table 2, Tj = 105C.
NVDD
VSS
RP
RN
Pad
Data
SW1
SW2
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