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| 型號(hào)： | MPC8245TZU350D |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 44/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 350MHZ 352-TBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 350MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤(pán) |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
49
System Design
Figure 26. COP Connector Diagram
HRESET 7
HRST_CPU
HRST_CTRL
From Target
Board Sources
COP_HRESET
13
SRESET 5
NC
11
VDD_SENSE
6
5 2
15 3
1 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
OVDD
CHKSTOP_IN 6
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
COP_TRST
7
16
2
10
12
(if any)
CO
P
Header
14 4
Key
QACK 1
OVDD
10 k
Ω
OVDD
TRST 7
10 k
Ω
OVDD
10 k
Ω
10 k
Ω
MPC8245
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No pin
COP Connector
Physical Pin Out
0
Ω 8
Note:
1 QACK is an output and is not required at the COP header for emulation.
2 RUN/STOP normally found on pin 5 of the COP header is not implemented on the MPC8245. Connect pin 5 of the COP
header to OVDD with a 1-kΩ pull-up resistor.
3 CKSTP_OUT normally on pin 15 of the COP header is not implemented on the MPC8245. Connect pin 15 of the COP
header to OVDD with a 10-kΩ pull-up resistor.
4 Pin 14 is not physically present on the COP header.
5 SRESET functions as output SDMA12 in extended ROM mode.
6 CHKSTOP_IN functions as output SDMA14 in extended ROM mode.
7 The COP port and target board should be able to independently assert HRESET and TRST to the processor to control
the processor as shown.
8 If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header through
an AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to
TRST of the part through a 0-
Ω isolation resistor.
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