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參數(shù)資料
| 型號： | MPC745CVT350LE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU HIP4DP 350MHZ 255-PBGA |
| 標準包裝： | 60 |
| 系列： | MPC7xx |
| 處理器類型： | 32-位 MPC7xx PowerPC |
| 速度： | 350MHz |
| 電壓： | 2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 255-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 255-FCPBGA（21x21） |
| 包裝： | 托盤 |
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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
41
System Design Information
Table 18 summarizes the signal impedance results. The driver impedance values were characterized at 0°,
65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus
voltage.
8.6
Pull-Up Resistor Requirements
The MPC755 requires pull-up resistors (1
5kΩ) on several control pins of the bus interface to maintain
the control signals in the negated state after they have been actively negated and released by the MPC755
or other bus masters. These pins are TS, ABB, AACK, ARTRY, DBB, DBWO, TA, TEA, and DBDIS.
DRTRY should also be connected to a pull-up resistor (1
5kΩ) if it will be used by the system; otherwise,
this signal should be connected to HRESET to select NO-DRTRY mode (see the MPC750 RISC
Microprocessor Family User’s Manual for more information on this mode).
Three test pins also require pull-up resistors (100
Ω1kΩ). These pins are L1_TSTCLK, L2_TSTCLK,
and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal
machine operation.
In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1
5kΩ) if it is used
by the system.
During inactive periods on the bus, the address and transfer attributes may not be driven by any master and
may, therefore, float in the high-impedance state for relatively long periods of time. Since the MPC755
must continually monitor these signals for snooping, this float condition may cause additional power draw
by the input receivers on the MPC755 or by other receivers in the system. These signals can be pulled up
through weak (10-k
Ω) pull-up resistors by the system or may be otherwise driven by the system during
inactive periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not
necessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:31],
AP[0:3], TT[0:4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in progress and, therefore,
do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require
pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The
data bus signals are: DH[0:31], DL[0:31], and DP[0:7].
If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled,
and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode,
these pins do not require pull-up resistors, and should be left unconnected by the system to minimize
possible output switching.
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
Table 18. Impedance Characteristics
VDD = 2.0 V, OVDD = 3.3 V, Tj = 0°–105°C
Impedance
Processor Bus
L2 Bus
Symbol
Unit
RN
25–36
Z0
Ω
RP
26
–39
26–39
Z0
Ω
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